The high-speed readout and low power consumption are important parameters to consider in designing CMOS image sensors. However, there is a trade-off between the high-speed readout and low power consumption. The demand for CMOS image sensors with more and more pixels leads to an increased bandwidth of readout circuitry in order to read out the increased number of pixels within a short frame of time. To facilitate the high-speed readout of large pixel array without consuming much power, therefore, a column-parallel architecture may be used.
In a column-parallel analog-to-digital converter (ADC) architecture of the CMOS image sensor, a single-slope ADC is often used because it can be implemented using a very simple column circuit and requires much less chip area than other types of ADC.
Recently, a multi-sampling technique has been proposed to improve a noise cancellation performance in the CMOS image sensor by sampling an input signal multiple times and analog-to-digital converting and by averaging sampled input signals.
The single-slope ADC device, however, is often accompanied with an increase in the number of clocks to sample an input signal multiple times and analog-to-digital convert the sampled input signals. For instance, a 10-bit analog-to-digital conversion requires 1024 clocks, and thus a 10-bit multi-sampling analog-to-digital conversion may require at least 2048 clocks. Such an increase in the clock cycles for processing reduces the image processing speed of the imaging device and thus is undesirable.
As an alternative to the multi-sampling technique discussed above, a multi-sampling operation can be performed by increasing a slope of a ramp signal by multiple times, e.g., ranging from ×1 to ×16, during the 1024 clocks to perform the 10-bit analog-to-digital conversion. As the slope of the ramp signal increases, however, it becomes more difficult to settle the ramp signal properly.
Since a noise performance is an important factor for maintaining a satisfactory imaging performance at a low illuminance, the ADC converter often uses different types of ramp signal generation devices including a ramp signal generation device for a low illuminance and another ramp signal generation device for a high illuminance. For example, if an input signal is within 300 least significant bit (LSB) of a whole reference value of 1024 LSB, its illuminance condition is identified as a low illuminance, and thus an analog-to-digital conversion is performed by multi-sampling the ramp signal three times with the slope of 1-300 LSB. If the input signal is over 300 LSB of the whole reference value of 1024 LSB, its illuminance condition is identified as a high illuminance, and thus an analog-to-digital conversion is performed by sampling the ramp signal with the slope of 1-1024 LSB.
Various implementations of the above-described technology, however, tend to exhibit a non-linear characteristic due to a characteristic difference between the two different ramp signal generation devices.
As a different approach, a double analog-to-digital conversions may be performed by driving two ramp signals outputted from two different ramp signal generation devices are driven through different buffers having different offset values. The two ramp signals have multiple crossings with an input signal, and the crossings occur sequentially with a predetermined delay.
However, it is difficult to guarantee a characteristic difference (e.g., a temperature variation) and an offset generation of each buffer.